Semiconductor Recovery & Vision For Future- Symposium Report Attached03/06/2010 - 03/06/2010

 

Time:     March 6, 2010 (Saturday); 1:00pm-5:00pm

Venue:    Intel SC12 Auditorium, 3600 Juliette Ln., Santa Clara, CA 95054

 

With global economy still being deeply in recession, the high tech industry in Silicon Valley has already been positioned for a strong recovery.  At the heart of today’s information technology, semiconductor technology is undergoing a new round of innovations driven by future demands from hardware to software applications. The Moore’s Law continues to advance, but with increasing challenges, where process and design are required to be co-optimized to achieve the best scaling benefit. Recent technology breakthrough in nano-scale lithography has unveiled future direction for semiconductor fabrication. Targeting to achieve higher performance with more efficient computing, the computing paradigm is experiencing a big reform from traditional frequency driven pipelining techniques to either multi-core homogenous computing with massive parallelism, or highly integrated system-on-chip solutions with heterogeneous computing. Multi-core architectures are both platforms and targets for future IC design, as well as the kernels for future throughput computing for data center applications.

Distinguished Speakers and Symposium Topics:

Dr. Daniel Tracy, Sr. Director of Industry Research & Statistics, SEMI
“Recovery in the Semiconductor Industry”
Dr. Peng Bai, VP of Technology and Manufacturing Group, Intel Corporation
“Advancing Moore’s Law: Technological Challenges and Economic Considerations”
Dr. Xiang Zhang, Ernest Kuh Endowed Chair Professor, UC at Berkeley
“Superlens and Plasmonic Lithography”
Dr. Charlie Huang, Sr VP & Chief Strategic Officer, acting CTO, Cadence Design Systems Inc.
“Design Methodology is Key to SoC Success”
Dr. Charles Fan, Sr. VP of R&D, Chairman of China Center of Excellence, EMC Corporation
“Data: Center of the Future Data Center”

 

Notice of using Intel Facility by CASPA:

Parking Regulation: Symposium parking will be at Intel SC9’s parking garage & open space parking lot (MAP)

Access at Intel Facility: During Symposium hours, attendees are allowed to stay ONLY in the Auditorium on the 1st floor and the front lobby of SC12. No access to other locations at Intel SC12 Building is permitted. The auditorium and front lobby will be closed for access after the event. Intel employees are not permitted to enter the building themselves, nor to bring in friends via front lobby security door in SC12. If they need to go inside the building, they must follow standard procedures and go to the security post at the rear of the building nearest the garage.

 

Online Registration: Please follow the instructions in the attached flier or click the link below:

 

CASPA 2010 Spring Symposium Online Registration Form

Please kindly register on line before 3/3.

 

In the bottom, plese find attached final presentation slides in pdf format, and the Symposium report.
AttachmentSize
CASPA_SpringSymposium_2010_SpeakersProfile.pdf416.58 KB
CASPA_2010_Spring_Symposium_1_Tracy.pdf167.85 KB
CASPA_2010_Spring_Symposium_3_Zhang.pdf3.85 MB
CASPA_2010_Spring_Symposium_4_Huang.pdf2.03 MB
CASPA_2010_Spring_Symposium_5_Fan.pdf720.66 KB
CASPA_20100306_Spring_Symposium_Report.doc32 KB

Time:

01:00:00

Location:

Intel, SC12 Auditorium, 3600 Juliette Ln., Santa Clara, CA 95054


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