Staff/Senior ASIC Verification Engineer

Title Staff/Senior ASIC Verification Engineer
Company Intersil
Location

Chengdu, China

Description

Job Description:
At this position, engineers are responsible for bringing up ASIC reusable verification environments. The engineer will interact with logic design engineers to create test plans for full chip and sub-modules verification. In addition, the engineer will define and implement code coverage plans, and develop test methodologies for new verification flow. 

Requirement

•    Bachelor or above from computer science, electronic, auto control, or related
•    3+ years or above experience in ASIC/complex SoC verification
•    Familiar with HDL languages, simulation tools and testbench design
•    Experience related to video/audio encode/decode
•    Proficient with high level verification languages such as System Verilog and Specmane
•    Experience with multimedia SOC platform a plus
•    Strong problem analysis and solving skills
•    Good team working interactive skills

Contact

Intersil is an Equal Opportunity Employer
For more information, or to apply, visit http://www.intersil.com/careers/jobsearch.asp