Senior Layout Engineer

Title Senior Layout Engineer
Company Intersil

Hyderabad, India




•    B.Sc. – Electronics, B.Tech./BE – Electronics/Computers, Diploma – Electronics/Computers
•    4 - 6 years of experience as Analog Mask (Layout) Design Engineer
•    Cadence Virtuoso/Virtuoso-XL Layout editor
•    Assura/Calibre Physical Verification tool
•    Experience in Floor-planning, Placement, Power routing, Schematic driven Layout, Layout verification (DRC and LVS), Parasitic extraction
•    Knowledge and Hands on experience of basic analog blocks such as op-amps, comparators, Bandgaps, VR's etc. is must
•    Knowledge on analog layout techniques and guidelines is must
•    Knowledge on Parasitic analysis, Current densities, Matching, ESD, Latch-up prevention and Isolation techniques is must
•    Understanding the impact of the layout on yield is must
•    Full Chip tape-out experience which includes final DRC, LVS, ERC, antenna checks and release to foundry is must
•    Debugging experience of DRC and LVS errors by analyzing rule decks is plus
•    Knowledge on triple well process and high voltage device layouts is must
•    Excellent communication skills and should be able to work within a team
•    Knowledge on basic analog circuit design concepts is plus
•    Scripting with cadence environment (SKILL programming) and tool automation experience is a plus


Intersil is an Equal Opportunity Employer
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