Engineer, Staff Layout

Title Engineer, Staff Layout
Company Marvell
Location

Santa Clara,CA

Description

The person will responsible for chip top level integration support for different SOC under tight project schedule. It requires strong knowledge on various issues on backend design flow to achieve high efficiency and reliability of result. 

Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool (Calibre) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro).

Requirement

Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool (Calibre) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro).

The candidate will have a BS Degree or diploma of layout training course.
Understanding detailed layout of transistor,resistor,capacitor and diode.
Understanding of analog layout such as device matching, common-centroid,P/G rail separaton, wire shielding, cross-coupling.
Must be familiar with DRC/LVS verification tools.
Must be familiar with Unix OS. Experience with Candence or Silicon Canvas layout tools is a plus.

Contact

Please go to https://www.marvell.apply2jobs.com/ProfExt/index.cfm?fuseaction=mExternal.showJob&RID=6580  and follow the instruction to submit your resume.