Engineer, Senior ASIC Design Verification

Title Engineer, Senior ASIC Design Verification
Company Marvell

Santa Clara,CA


The candidate will join the wireless verification team and be responsible for the thorough verification of our next generation wireless chips. He/she will be responsible for developing verification plans, building and setting up verification environments, modeling and co-simulation, testvector generation, at the IP block and chip levels. The job expects the candidate to be involved from chip definition to silicon tapeout and bring up.


This position requires a minimum of 7 years of experience in the verification of chip designs. A MSEE or PhD EE is required. Experience in the development of wireless technologies is desired. Candidate should be familiar with some of the following; Verilog, VCS/NCsim, Modeltech, C-language or SystemC, Vera, Specman, System Verilog. Candidate must show a strong knowledge in the development of chip verification environments and a proven track record of taping out chips to production. Candidate focused expertise in CPUs, high-speed peripheral interfaces (PCI-E/USB), or any networking technology beyond verification knowledge is definitely a plus. VMM/OVM/system verilog exposure a huge plus.


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