Engineer, Design For Test (DFT)

Title Engineer, Design for Test (DFT)
Company Marvell
Location

Santa Clara,CA

Description

Participate in design, verification & debug of highly integratedSOC designs for wireless networking applications, with particular 
emphasis on entire DFT strategy. Includes design & verification of dedicated DFT components, detailed knowledge of DFT tools such 
as ATPG, BIST, pattern generation and silicon debug. Good communicationskills needed as the candidate is required to work closely with other design engineers within the group & also externalgroups such as CAD, test engineering and product engineering.

Requirement

BS EE with 4+ years experience of deep submicron SOC design and verification. Analytical problem solving a must, together with
good knowledge and familiarity of full ASIC design flow and DFT specific tools/techniques. Both written & verbal communication skills important.

Contact

Please go to  https://www.marvell.apply2jobs.com/ProfExt/index.cfm?fuseaction=mExternal.showJob&RID=6437 and follow the instruction to submit your resume.