Senior Engineer

Title Senior Engineer
Company Marvell

Santa Clara,CA


Electronic Engineer with a BS plus 6 years of experience or equivalent. Experienced in logic circuit design and transistor level layout. The position requires experience in circuit sizing for standard cell libraries, low power libraries as well as the impact that circuit sizing has on layout parameters for area, timing, reliability trade-off. The person is expected to influence library cell architecture and trade-offs including low power design, area/speed trade-off, base library height trade-offs, etc. The position also requires close supervision of layout designers to ensure final layouts are consistent with target parameters. Experience with 40nm or smaller technology is required.

The person should be experienced in automating cell level design flow to increase overall productivity in library development. The person should have good software skills in Linux/Unix utilities including Makefiles, shell scripting, and Perl coding. The person should be knowledgeable in HSPICE (and compatible simulators), Laker, Virtuoso, Calibre DRC/LVS/LPE, StarRC-XT, etc. Experience in library characterization tools and liberty file syntax is desirable.


EE with at least 6 years of experience in the standard cell circuit design field.


Please go to  and follow the instruction to submit your resume.