[CIE-SF] EPMC Seminar07/22/2014 - 07/22/2014

[CIE-SF] EPMC Seminar

 

 

The EPMC (Electronics Packaging and Manufacturing Committee) Group of CIE/USA-SF and co-sponsor ITRI International will hold the July Seminar featuring “A Tribute to Moore and Dennard” and “Lead Frame Package Design flow using CDS Electronics Packaging Designer”.  All CIE/USA-SF members and non-members are cordially invited to attend this very informative seminar.


Topic1: “A tribute to Moore and Dennard" by Dr. Abe Yee

Topic2: “Lead Frame Package Design flow using CDS Electronics Packaging Designer (EPD) and Cadence Chip Package Design tools”  by Mr. Jian Wu
 
Date:  
July 22, 2014 (Tuesday) 7:00 - 9:00 pm (registration starts at 6:30pm)
(Cancel July 15) 

Venue:  
ITRI International, 2870 Zanker Rd., Suite #140, San Jose, CA 95134.  (Free parking)
 
Admission:  
Free admission for CIE-SF members, $5 for non-CIE-SF members
 
Registration:
Pre-registration on-line is required:  Please click here to register on-line.
 

CIE/USA-SF membership:
Please visit http://www.cie-sf.org/membership to join CIE-SF membership and enjoy discounts to all CIE-SF events.
 
Co-Sponsor:
ITRI International, Inc.
 
Detail Abstract and Bio:
A tribute to Moore and Dennard
 
Abstract:
Gordon Moore and Robert Dennard put forth the roadmap that propelled the semiconductor industry to where it is today.  But with CMOS scaling slowing significantly and questions about the future of the industry it’s time to look back at the accomplishments, how far we have gone, what the issues are and where we go from here. 
 
Bio:
Abe Yee is currently Sr. Director of Advanced Technology and Package Development at NVIDIA Corporation. His current responsibilities include path finding and benchmarking technologies, investigating new technologies and setting NVIDIA's packaging roadmap for both GPU and Mobile products. From 2000-2002 he was Director of Engineering at SUN Microsystems responsible for SPARC processor manufacturing and reliability. He served as VP of Operations at Equator Technologies from 1996-2000 responsible for all aspects of development, NPI and production with manufacturing partners. From 1983-1996 he was at LSI Logic Corp, where he held various senior management roles in technology development and operations. Dr. Yee received his BA in Mathematics and Physics and his MA and PhD in Physics from UC Berkeley.
 
 
Lead Frame Package Design flow using CDS Electronics Packaging Designer (EPD) andCadence Chip Package Design tools


Abstract:  
Chip packaging using leadframes is undergoing a resurgence. This is due to several factors, cost, increased ability to package higher I/O chips and even multiple chips in a single low form factor leadframe package. However this has also created the need for DRC checking in 3D of closely spaced bondwires as well as a variety of specific leadframe package based manufacturing rules. Besides this, especially with higher frequency chips, the need to be able to port such designs to electrical analysis tools has become increasingly relevant. This presentation covers how these EDA requirements are being met by two companies coming together to jointly create a solution that addresses chip co-design , providing a variety of leadframe package manufacturing rule checks before exporting the design to analysis tools.


Bio: 

Jian Wu has worked in the semi-conductor industry for over 15 years specializing in the area of 2D and 3D image processing and component display component for wafer inspection and for the CAD design tool core database. In earlier years, Jian’s Intelligent Dynamic Traffic System was awarded the Best Project Award at the Fifth Annual IRIS/PRECARN Conference, Vancouver 1995. Jian has two Masters Degrees, the first from the Geo-Science University, China and the second from the University of Victoria, Canada.


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