Design For Test (DFT) Engineer

Title Design for Test (DFT) Engineer
Company Infineon Technologies Xi’an Co. Ltd.

Xi’an, China


Job Description:

Implement Design for Test strategy into the chip and responsible for DFT sign off. Participate in driving new DFT methodology and solutions to improve quality, reliability and in system test and debug capability.

• Working out DFT concept, aligning with designer.
• Implement basic DFT schemes in terms of BIST, scan, boundary scan on chip.
• Generate tests which achieve highest possible component test coverage with lowest overhead.
• Verify all DFT logics and test patterns with simulation and static timing analysis tool.
• Implement and verify advanced DFT logics like logic BIST, high speed interface test logic etc.
• Participate in new DFT methodology discussion and solution generation.
• Work with design team.



• Typically requires MSEE/CS combined with 5+ years experience, or BSEE/CS combined with 7+ yrs experience.
• Good knowledge in Design for Test in general. Understand the concepts of BIST, SCAN, JTAG, ATPG.
• Experience in DFT design, Testability, and Reliability issues.
• Hands on familiarity with various DFT analysis, and verification tools.
• Hands on knowledge of simulation and verification debug tools.
• Good knowledge of test engineering in terms of test program generation, understanding of testers and associated hardware is a plus.
• Working knowledge using Verilog HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
• Experience in complete DFT flow from beginning to tapeout.
• Excellent written and verbal communications, team and people skills.