Logic Physical Synthesis Engineer

Title Logic Physical Synthesis Engineer
Company Infineon Technologies Xi’an Co. Ltd.
Location

Xi’an, China

Description

Job Description :

• Interface with IC Design/Verification team (timing and power constraints definition)
• Writing, running, optimization of logic and physical synthesis scripts
• In-depth knowledge of STA. Ablility to handle timing analysis for multiple modes and corners
• Physical design Floor planning, place & route, clock tree synthesis, routing cleanup
• Power IR & EM analysis
• Parasitic extraction/SPEF/SDF generation
• Prime Time/ICC STA correlation
• Formal Verification (Equivalence checking)
• Physical Verification (DRC, ERC, LVS, ANTENNA)
• Deep understanding of DSM effects (sub 90 nm experience preferred)

Requirement

Requirements:

• Masters/Bachelor’s Degree in Electrical/Electronics Engineering or in related field
• Tool skills:
• Synopsys Design Compiler and Power Compiler
• PERL, TCL languages
• Prime Time and constraint creation/modification
• IR analysis tool such as PrimeRail
• Synopsys ICC experience preferred
• Calibre and/or Assura
• Formal Verification tool
• Knowledge of VHDL or Verilog is a plus
• RTL Hand-off checks (SpyGlass) and Design Doc. is necessary
• Ability to speak and write English is a must, CET 6
• Self-motivated team player and able to work with minimum supervision
• Minimum 2 years of physical design and timing closure experience
• Willingness to take overseas business trip

Contact

联系方式:hr-xian@infineon.com