CIE/USA-SF EPMC Workshop: 2.5D/3D Solution Workshop03/07/2015 - 03/07/2015



2.5D/3D Solution Workshop

Information technology has experienced revolutionary progress over the past several decades.  Escalating demand for electronic devices with improved performance, functionality and mobility has compelled innovative enabling technologies in packaging technology, thus evolving from conventional board level assembly to two types of system-level integration:  System on Chip (SoC) and System in Packaging (SiP).  However, both integration technologies are already fast approaching their physical limits in addressing contemporary and future demands due to their limited interconnect bandwidth.
Through Silicon Via (TSV) technology holds the key to eliminating chip-to-chip interconnect constraints and the potential to enable new disruptive architectural solutions.
This half-day workshop will cover recent developments in enabling technologies for 2.5D/3D solutions based on TSVs, and design processes of 2.5D/3D technology including electrical, mechanical and thermal issues. 
Date:   March 7, 2015 (Saturday) 13:00 – 17:00 pm

Venue:   Cadence Auditorium, Building 10, Cadence, 2665 Seely Avenue, San Jose, CA 95134
Direction:    The easiest way is to enter from the Montague Expwy/Trimble Rd traffic light.  Building 10 is the tallest 5-story building in the Cadence campus.

Admission:   Free admission for all the attendance.
CIE/USA-SF membership:
Please visit to join CIE-SF membership to enjoy discounts for all future CIE-SF events.
13:00 -13:30   Sign in
13:30 - 14:10 Recent Developments for Enabling 2.5D Solutions, Dr Dongkai Shangguan
14.10 - 14.50   FPGA SSI Technology Design and Verification, Mr Yong Wang
14.50 - 15.30   Thermal Analysis for 2.5D/3D IC Designs, Mrs Yun Dai
15.30 - 15.40   Coffee Break
15.40 - 16.20   The Adoption of 2.5D and 3D Packaging Technology, Dr Larry Zu

16:20 - 17:00 TCAD Solution for Managing Mechanical Stress in 3D IC structures, Dr Xiaopeng Xu

Event Flyer: Link